1. Technical Field
A method for fabricating a semiconductor device is disclosed and, more particularly, a method for fabricating a semiconductor device that prevents degradation of the semiconductor device caused by damage to an insulation layer during a process for forming an opening for a storage node contact.
2. Description of the Related Art
There have been numerous attempts at achieving higher integration and higher performance of semiconductor devices. With respect to the higher integration, it is essential to develop technologies for obtaining contact regions as well as for enhancing gap-filled properties.
FIG. 1 is a plan view schematically illustrating a conductive pattern including a word line for forming a bit line and the bit line. In FIG. 1, a plurality of gate electrodes, e.g., word lines W/L, are aligned in one direction, and a plurality of bit lines B/L are aligned in another direction to thereby cross or intersect the word lines W/L. A plurality of landing plug contacts (LPCs) are first formed by a LPC1 process. A bit line B/L is contacted to an active region (not shown) of a substrate through one of landing plug contacts (LPC) and a bit line contact (BLC). Some of the LPCs are coupled to storage node contacts (SNCs) in order to form storage node capacitors.
FIGS. 2A to 2F are cross-sectional views along lines X-X′ and Y-Y′ of FIG. 1. FIGS. 2A to 2F show a method for fabricating a semiconductor device according to the prior art.
Referring to FIG. 2A, a gate electrode 11 is formed on a substrate 10 containing various elements of the semiconductor device. Specifically, the gate electrode 11 is formed with a single or stack layer of tungsten or polysilicon. A gate insulation layer (not shown) is formed at an interface between the gate electrode 11 and the substrate 10. On top of the gate electrode 11, a nitride- based hard mask (not shown) having a different etch selectivity ratio from an oxide-based inter-layer insulation layer is formed to protect the gate electrode 11 during a self align contact (SAC) process and to obtain an appropriate etch profile during the SAC process.
Next, such technique as an ion implantation technique and so forth is performed to form an impurity adhesion layer such as a source/drain adhesion, i.e., the active region (not shown), on a portion of the substrate 10 between the gate electrodes 11. A nitride-based insulation layer 11′ for a spacer (hereinafter referred to as spacer insulation layer) is formed in such a manner to encompass lateral sides of the gate electrode 11.
Referring to FIG. 2B, a typical oxide based material or a flowable oxide material is used to form a first inter-layer insulation layer 12 of which top portion is planarized. An anti-reflection layer (not shown), especially, an organic anti-reflection layer is coated on top of the first inter-layer insulation layer 12. Then, a photoresist is coated on the anti-reflection layer and, a photolithography process is performed with use of a light source of KrF or ArF to form a first photoresist pattern 13 for forming LPCs.
The photoresist is coated on the anti-reflection layer with a predetermined thickness. Afterwards, a predetermined portion of the photoresist is selectively photo-exposed by using a light source such as ArF (not shown) and a predetermined reticle (not shown). Subsequently, a developing process is performed on the remaining portions. Remnants generated after performing a subsequent etch process are removed through a cleaning process to thereby form the first photoresist pattern 13 (FIG. 2B).
After the photoresist coating, an additional process such as an electron beam scanning or an ion implantation of Ar is performed to strengthen the tolerance of the first photoresist pattern 13 to a subsequent etch process.
Next, the first inter-layer insulation layer 12 is selectively etched with use of the first photoresist pattern 13 as an etch mask. Then, a LPC1 process is performed to expose a surface of the substrate 10 to form the contact holes shown at 14.
The first photoresist pattern 13 is removed through a photoresist strip process, and etch remnants existing within the contact hole 14 are removed by a cleaning process. Then, a contact material is contacted to the contact hole 14 by using a polysilicon deposition or a selective epitaxial silicon growth technique. Afterwards, a chemical mechanical polishing (CMP) process or a blanket-etch process forms the isolated plugs 15 shown in FIG. 2C.
Referring to FIG. 2D, a second inter-layer insulation layer 16 is formed on the above structure including the plugs 15, and a second photoresist pattern 17 for defining a bit line contact is formed. The second inter-layer insulation layer 16 is selectively etched by using the second photoresist pattern 17 as an etch mask so that a bit line contact hole 18 is formed that exposes a surface of the plug 15.
Next, as seen in FIG. 2E, a bit line contact plug 19 contacted with a surface of the opened plug 15 is formed, and then, a bit line 24 is formed by stacking a nitride based hard mask 21 on a layer 20 made of tungsten, tungsten nitride or polysilicon.
Turning to FIG. 2F, a third photoresist pattern 22 is formed for exposing a surface of the plug 15 for a SNC. The photoresist pattern 22 is then used as an etch mask when the second inter-layer insulation layer 16 is selectively etched. From this selective etch of the second inter-layer insulation layer 16, storage node contact holes 23 are formed.
Meanwhile, in case of a LPC2 process for forming SNCs, the typical SAC process is used. Thus, an etch profile of the storage node contact hole 23 is sloped and is narrower toward the bottom of the hole 23. As a result, in addition to the typical SAC process, a wet-type etch process is simultaneously performed during the LPC2 process in order to prevent any increase in the contact resistance. Consequently, it is possible to secure a contact area, i.e., a critical dimension (CD).
However, the first and the second inter-layer insulation layer 12 and 16 typically use oxide layer materials, e.g., boro-phospho-silicate glass (BPSG), and these materials have a higher etch ratio to a buffered oxide etchant (BOE) or HF which are both used in the wet-type etch processes. Because of this high etch ratio, as shown in FIG. 2F, the first inter-layer insulation layer 12 is prone to an attack or erosion shown at 26.
The erosion 26 can induce an electric short with the storage node, bit line or other conductive wires, thereby deteriorating performances of the semiconductor device.
FIG. 3 is a diagram further illustrating problems arising in the prior art. As shown, during a formation of a nitride layer 25 for producing a spacer for the bit line 24 (hereinafter referred to as bit line spacer), voids 26 occur at a portion where the erosion 26 to the first inter-layer insulation layer 12 is generated. This void effect becomes a critical factor that gives rise to an electric short between the electrodes and reduces yields of the semiconductor devices.
In order to prevent the erosion shown at 26, one method decreases the CD of the first inter-layer insulation layer 12 during the LPC1 process. However, this technique is practically impossible due to difficulties in obtaining sufficient spaces for isolating each device and in applying the SAC process.
Furthermore, it is difficult to increase the width of the bit line in practice due to difficulties in obtaining a CD of the bottom side of the contact and a deterioration of the gap-fill properties during the storage node contact formation process.
Accordingly, it is necessary to develop a technology capable of preventing the attack or erosion of bottom layers caused by wet-type etching performed in the course of storage node contact formation.